一、ap_memory axilite axi_stream架构二、代码框架void param_array_top(hls::streamap_uint32 src,hls::streamap_uint32 dst,ap_uint32 param_cfg[128]//axilite_ap_memory,generate bram logic){#pragma HLS RESOURCE variableparam_cfg coreRAM_2P_BRAM#pragma HLS INTERFACE axis register both portsrc#pragma HLS INTERFACE axis register both portdst#pragma HLS INTERFACE s_axilite portreturn bundleCONTROL_BUS#pragma HLS INTERFACE s_axilite portparam_cfg bundleCONTROL_BUSstaitc ap_uint32 local_param_1;staitc ap_uint32 local_param_2;staitc ap_uint32 local_param_3;staitc ap_uint32 local_param_4;staitc ap_uint32 local_param_5;staitc ap_uint32 local_param[128];#pragma HLS RESOURCE variablelocal_param coreRAM_2P_LUTRAMlocal_param_1 param_cfg[0];local_param_2 param_cfg[1];local_param_3 param_cfg[2];local_param_4 param_cfg[3];local_param_5 param_cfg[4];kernel_process(src,dst,param_cfg[0],local_param_1);}void kernel_process(hls::streamap_uint32 src,hls::streamap_uint32 dst,ap_uint32 param_cfg[128],ap_uint32 local_param_1){#pragma HLS DATAFLOWread_stream();proc_stream();write_stream();}